Results

Project Demonstration

1 VGA

The VGA works as intended where there is 2-bit resolution for each color. Theoretically, that means we have access up to 64 colors. The hSync and vSync signals contributing to the VGA’s timing are extremely accurate. The VGA was one of the earliest specs completed in the project, and it has helped us debug other specs.

2 Camera Interface with I2C and SPI

Before the camera was scrapped from the project, I2C initialization and write functions worked as intended in setting up the output format. No unknown decoded bits were found while I2C transfered data. The SPI peripheral worked as intended in receiving pixel data from the camera module. However, the ouput data from the camera module was very inconsistent which can be attributed to the configuration setup within the two internal register banks. We manually configured registers by looking at the datasheet, and used a library available to the public. However, the camera’s reliability did not change. We do not use I2C now, but we still use SPI and it works properly.

3 Sobel Edge Detection Algorithm

The Sobel edge detection implementation proved highly successful, demonstrating both accuracy and exceptional performance. By leveraging the FPGA’s parallel processing capabilities and implementing a 5-stage pipeline architecture, we achieved processing speeds of one pixel per clock cycle. The edge detection quality was enhanced by using a lookup table stored in BRAM for fast square root calculations, and the 2-bit compression scheme effectively preserved edge detail while optimizing memory usage.

The algorithm successfully identifies edges across different image intensities, using carefully calibrated thresholds (21, 42, and 63) to maximize the dynamic range of the output. The SPRAM storage system handled the processed image data without any timing violations, ensuring smooth display output to the VGA monitor.

The hardware acceleration provided by the FPGA made the edge detection significantly faster than what would be possible with software-only implementation on the MCU, demonstrating the advantages of our hardware/software partitioning approach.

4 DMA and Double Buffer

Before the camera was scrapped from the project the DMA and double buffer system worked worked well. In total, three DMA channels were utilized (2x memory to peripheral and 1x peripheral to memory). The first memory to peripheral DMA transaction sends clock and read fifo command packets to the camera module. The one and only peripheral to memory DMA transaction used a doubler buffer system to avoid overwriting data. A handful of pointers were used in this operation, and data transfers worked seamlessly within memory. The final DMA channel took the preprocessed pixel data and sent it over SPI successfully. However, the camera module was scrapped from the project, so we are not using the DMA controller nor double buffer system currently.

5 SPRAM, BRAM, and SPI on FPGA

The SPRAM, BRAM, and SPI on the FPGA work as intended. The square root look up table fits nicely within the BRAM. The SPRAM holds the entire edge detected image without conflict, and it can be read and written to without causing any setup time violations when synthesized.